With the explosive demand for AI computing power, the bandwidth requirement of server data buses has risen sharply. Taking PCIe as an example, the protocol has evolved to PCIe 6.0/7.0, with signal rates reaching 64GT/s and moving toward 128GT/s. The channel configuration is expanded to x16, achieving ultra-large bandwidth communication by increasing frequency and parallelism.
Meanwhile, the soaring signal frequency leads to an exponential increase in PCB insertion loss, causing signal attenuation and distortion. Impedance discontinuity of PCB traces will introduce reflection and timing jitter, which together cause signal integrity issues.
PCIe Specification Evolution
To achieve ultra-high-speed data transmission up to 128GT/s and address the stringent insertion loss and impedance design challenges, PCIe 7.0 has adopted a series of coordinated measures.
The core lies in continuing PAM4 modulation combined with advanced FEC technology, which significantly improves signal robustness and anti-interference capability. In addition, adaptive equalizers are introduced to dynamically compensate for the frequency response distortion of the transmission link, effectively offsetting the impact of insertion loss.
In terms of physical layer design, low-loss high-speed PCB materials are adopted, and the impedance tolerance is controlled within ±3% to ±5% to reduce signal attenuation.
At the package and interface level, the connector design is optimized to shorten signal paths and reduce crosstalk, thereby minimizing signal reflection and loss.
Insertion loss in a PCB refers to the attenuation of signal strength (power) when a signal passes through PCB transmission lines (such as traces, vias, etc.), usually measured in decibels (dB).
Requirements of PCIe 7.0 for Signal Link Loss
Insertion loss essentially measures the energy loss of a signal during propagation. It is a key indicator for evaluating signal integrity in high-speed communication systems, mainly composed of the following types of losses:
On high-frequency and high-speed PCBs, conductor loss is usually dominant.
As the signal frequency increases, high-frequency current tends to flow on the conductor surface, reducing the effective conductive cross-sectional area and increasing resistance. The higher the frequency, the shallower the skin depth and the greater the loss.
A rough copper surface forces the current path to become longer and tortuous, generating parasitic inductance and significantly increasing resistance and loss at high frequencies. Using smoother copper foils (such as HVLP) can reduce this loss.
Conductor loss, significantly affected by skin effect and copper surface roughness at high frequencies, causes signal energy to dissipate in the form of heat.
Effect of Copper Foil Roughness on Signal Integrity
When a signal propagates in a PCB (dielectric material), molecules or dipoles in the dielectric material polarize and relax following the change of the electric field direction, converting part of the electrical energy into heat. This part of the loss is called dielectric loss. Simply put, part of the signal energy is absorbed by the PCB substrate.
Dielectric loss depends on the dissipation factor (Df, also known as loss tangent tanδ) of the substrate material. The higher the Df value, the greater the dielectric loss.
The loss is proportional to frequency; the higher the frequency, the greater the dielectric loss.
Selecting “low-loss” high-speed materials with lower Dk (dielectric constant) and Df is the key to reducing dielectric loss.
Conductor Loss and Dielectric Loss at Different Frequencies
Radiation loss is the loss caused by signal energy radiating from the transmission line structure to the surrounding environment in the form of electromagnetic waves.
A transmission line acts somewhat like an inefficient antenna.
The higher the frequency, the easier it is to radiate and the greater the loss.
Microstrip lines (signals on the surface with exposed fields) are more prone to radiation loss than striplines (signals buried between two ground planes).
Thicker substrates and lower dielectric constants will increase radiation loss.
It is particularly obvious at impedance discontinuities (such as connectors, vias) and signal emission areas.
A Vector Network Analyzer (VNA) is the most convenient instrument for measuring insertion loss. Each port contains a signal source and a receiver. We can send a signal from port 1 to the device under test, and the receiver at port 2 measures the output signal processed by the device under test. The VNA directly compares and displays the difference between the output and input signals, which is the direct measurement of the S21 parameter (forward transmission coefficient), intuitively reflecting the loss from input to output.
The Delta-L method was developed by Intel. By designing two transmission lines of different lengths, testing their S-parameters, and then performing fitting calculations and difference operations, the insertion loss per unit length is obtained.
Compared with direct division, Delta-L mathematically eliminates the influence of lead-in/lead-out such as test fixtures, probes, and vias when calculating the difference, so as to calculate the insertion loss per inch of pure trace segments on the target PCB layer. It significantly improves accuracy and stability especially in high-speed and high-frequency scenarios, and has become the mainstream method for PCB mass production testing.
Delta-L Insertion Loss Test Method
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